IBM Creators Take the Stand in Upping Battery Life, Performance With Future 5nm Silicon Chips


Back in 2015, IBM unveiled a 7nm process in manufacturing smaller, faster processors. An interesting move for IBM, or in the very least, a highly impressive one. Intel has always ruled in this area. The tech giant is of course known as one who create processors as thin and powerful as physically possible. When IBM announced the world’s first functional 7nm node test chip, it was a big deal, as the world was used to a computer processor built with a 14nm process. After IBM’s astonishing revelation, thoughts resonated that the next-in-line would open the door to 10nm chip production by the year 2016. Yet, the challenges associated with this notion of shrinking manufacturing processes any more are highly relevant. If there’s anything difficult to rush the process of, technology is definitely one of them.

Hence, the goals IBM set for itself were, and have been within means; and nothing too far from reach that the company's group of collaborators couldn’t fulfill dipping below even the 10nm chip. For example, shortly after realizing this futuristic CPU processor technology, the company did in fact encounter itself with a 9nm transistor demonstration, built out of carbon nanotubes, yet found the process to be a few years away from fruition. Here we are today, in 2017, and with IBM not just encountering improved chip manufacturing processes, but fortuitously wanting to go ahead building 5nm chips. Yes, this is real, and in partnership with Samsung and GlobalFoundries, IBM’s new chip design will use something called “gate-all-around” transistor (GAAFET). Getting quite technical here, what looks more like an x-ray at a dental office, is how the “gate material” wraps around in three horizontal “nanosheets”, which is different to the vertical design, a.k.a. FinFET used in state-of-the-art chips.

This juncture, between IBM’s Research Alliance with GlobalFoundaries and Samsung, will start the process of manufacturing the 5nm chips by the year 2020. This may not be right around the corner, but this is partly due to Moore’s Law, the economic law named after Intel cofounder Gordon Moore that “predicts the number of transistors packed within one size of silicon should double every 2 years”, constantly being challenged. This is because it isn’t exactly simple to come up with fundamental breakthroughs right on time. While sectors of the chip industry may consistently be working on this, others are looking towards alternatives to cramming more transistors onto one chip, by rather changing the architectural design all together. In the end, IBM and its partners are one step closer to smaller 5nm chips. Since the nanosheets will offer a 40 percent increase in performance than what we are seeing today’s 10nm chips, this would mean the kind of performance to meet the future demand in AI, VR, wireless accessories, and mobile devices; all the while offering a 75 percent increase in power savings.

Topics: Technology News Inventions & Innovations

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